1. Field of the Invention
The present invention relates to a compressive sensing (CS) approach for reconstructing a signal x(t) that has been randomly and non uniformly sampled and digitized. More specifically, the present invention relates to an approach for reconstructing a signal obtained using a photonic TS ADC in conjunction with non uniform sampling (NUS) using CS techniques.
2. Discussion of the Related Art
Digitizing high frequency and/or high bandwidth signals is a desired operation. Apparatus requiring such operations include test and measurement equipment in laboratories, high speed data communications systems, and electronic support measure systems (ESM) that can demonstrate a high probability of intercept (POI), large dynamic range, and good sensitivity over a signal having a wide Instantaneous BandWidth (IBW). Such operations are also applicable to software-defined radio architectures that can unify common back-end digital processing for transceiver operations in e.g. an automobile.
A photonic TS ADC (Time-Stretch Analog-to-Digital Converter) can provide continuous time (CT) processing, while delivering a high Effective-Number-Of-Bits (ENOB) of >8 over an IBW of 10 GHz. FIG. 1 is a schematic diagram of a conventional (uniformly sampled) photonic TS ADC system.
The system of FIG. 1 implements multiple λ-channels to accomplish signal de-serialization before A/D conversion. The number of parallel λ-channels needed to accomplish CT A/D conversion in such a system is directly proportional to the stretch ratio M, where M=1+D2/D1. In simulations, photonic TS ADC systems with a large stretch-ratio M of M around 41 resulted in a digitized output signal having an effective number of bits (ENOB) that is >8 for an input signal frequency (fsig) of 10 GHz. A large stretch ratio (M) is important to producing a high ENOB. However, a TS ADC system constructed with a stretch ratio of 41 may require a large number of parallel channels to accomplish continuous time (CT) operation. Specifically, the number of parallel ADC-channels required to form a CT TS ADC system is directly proportional to M as illustrated in FIG. 1.
FIG. 2 is a schematic diagram of an ADC system termed a random demodulator (RD) described in a document from Tropp et al, entitled “Beyond Nyquist: Efficient Sampling of Sparse Bandlimited Signals”, IEEE Transactions on Information Theory, Vol. 56, No. 1, 2010”; for the compressive sensing of a wideband analog input-signal. In FIG. 2, an input signal f(t) is coupled to a first input terminal of a mixer 302, and a pseudorandom generator 304 is coupled to a second input terminal of the mixer 302. An input terminal of the pseudorandom generator 304 is coupled to a source of a seed value for controlling the pseudorandom sequence. An output terminal of the mixer 302 is coupled to an input terminal of an integrator 306. An output terminal of the integrator 306 is coupled to an input terminal of a sampler 308, where the components 306 and 308 behave the same way as a standard ADC. An output terminal of the analog-to-digital converter 306-308 generates a sampled digital output signal y[n].
To permit signal reconstruction via use of compressive sensing (CS), the analog input signal f(t) is assumed to be a frequency-sparse signal. As illustrated in FIG. 2, a pseudo-random chip-sequence pc(t) from pseudorandom generator 304, switched at a rate W between random amplitudes of ±1, is mixed in mixer 302 with the analog input signal f(t). The mixed signal is fed to integrator 306. The output of integrator 306 provides a randomized projection (i.e., a randomized linear combination) of the mixed product of f(t) and pc(t) over an integration time-interval of 1/R, where R is the clock rate of the cascaded ADC chip. Because the chip-rate of pc(t) is W, W/R randomized chips are mixed together (via integration) to form the input of a sampler chip 308 that follows the integrator 306 (the “chip-sequence” being the pseudorandom code-sequence pc(t) (typically ±1) generated by the Pseudorandom Generator in the figure and the chip-rate being the number of pulses/sec at which the code is generated.). It is to be noted that although there are Md row-elements in the “measured” output, each row-element is obtained, after integration, over successive sampling time-intervals nTs. The sampler 308 chip is clocked uniformly at a rate R. As detailed hereafter, CS based techniques are used to calculate sparse Fourier coefficients (‘a’ω of [a]) of f(t) from the measured output of the ADC 306, 308.
As detailed in the Tropp et al. document, compressive sensing (CS) techniques can use a matrix form model of the random demodulator (RD) of FIG. 2. FIG. 3 is a matrix diagram illustrating a CS matrix formalism representing the RD system architecture depicted in FIG. 2. CS based techniques can be used to calculate sparse Fourier coefficients (“a′ω” of [a]) of f(t) from the measured output of the ADC. The input signal xn is eventually recovered via use of a W×W DFT that transforms the sparse vector (denoted [a] in FIG. 3) back to the time-domain. The compression ratio of this random demodulation scheme is given by W/R. Because the sampling rate R of the ADC-chip can be much lower than the Nyquist sampling rate of the input signal f(t), the CS compression ratio of a RD can be >10. For example, an input harmonic signal f(t) at 800 kHz may be recovered from ADC measurements that are clocked at 100 kHz, which was 1/16 the Nyquist sampling rate fN.
The mixing of pc(t) and f(t) may randomize the amplitudes of the input signal (at the chip rate W) in the RD approach, and the sensing bandwidth of a RD architecture may be limited by that of the mixer.
FIG. 4 is a schematic diagram of an all-electronic approach for implementing NUS via use of a S/H and Pseudo Random Bit (PSRB) timing generator, such as described for example in a document from M. Wakin, et al, entitled “A Non-Uniform Sampler for Wideband Spectrally-Sparse Environments”, to be published in JESTCS”. In FIG. 4, a signal input terminal of a main sample-and-hold (MSH) circuit 502 is coupled to a source of an analog input signal Ain. An output terminal of the MSH circuit 502 is coupled to a signal input terminal of a subsampling sample and hold (SSH) circuit 504. An output terminal of the SSH circuit 504 produces an analog output signal Aout and is coupled to a signal input terminal of an analog-to-digital converter (ADC) 508. An output terminal of the ADC 508 generates a digital output signal Dout.
A first input terminal of a timing generator 506 is coupled to a source of a clock signal Cin, and a second input terminal of the timing generator 506 is coupled to a source of a sampling clock signal Nin. A first output terminal of the timing generator 506 is coupled to a timing input terminal of the MSH circuit 502; a second output terminal of the timing generator 506 is coupled to a timing input terminal of the subsampling S/H 504; and a third output terminal of the timing generator 506 is coupled to a timing input terminal of the ADC 508. One skilled in the art understands that other elements may be necessary for the proper operation of the system illustrated in FIG. 4, such as buffer amplifiers. The skilled practitioner will understand what those elements are, where they should be located, and how to design and build those elements. One skilled in the art further understands that the ADC 508 may be implemented by a commercial off-the-shelf component.
In operation, the analog input signal Ain is a frequency fsig having a bandwidth of around 0.8-2 GHz. This signal is digitized by subsampling randomly at an average rate (fs)AV of 0.236 GHz. The input signal is reconstructed from the ADC 508 output via use of compressive sensing techniques. The all-electronic NUS approach illustrated in FIG. 4 is implemented with a sample/hold (S/H) frontend, i.e. the main sample and hold MSH circuit 502, samples the input signal Ain at the Nyquist rate or higher. Samples are then randomly discarded, e.g. keeping on the average of one of every 19 samples, by the SSH 504 in response to a synchronized pseudo-random bit (PSRB) sequence from the timing generator 506 to simulate randomized NUS.
It is noted that the system of FIG. 4 is implemented with a Nyquist rate S/H, i.e. MSH 502, and it would be difficult to scale to a signal with a wider IBW without incurring clock jitter issues. In addition, the chip also uses on-grid A/D conversion, making it difficult to obtain performance advantages.
Improvements may therefore be made over the conventional systems discussed above. More specifically, an ADC system which can produce a digital representation of a frequency sparse signal which may have a wide instantaneous bandwidth, while maintaining a suitable of equivalent number of bits with a minimum of circuitry, is desirable. A CT ADC system using CS techniques designed with reduced channel count may decrease data-throughput along with simplified hardware construction. This, in turn, may facilitate the deployment of digital channelized receivers, reduce costs, and produce improved computational results.